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NOT RECOMMENDED FOR NEW DESIGNS
T3V3LCS3
LOW CAPACITANCE SURFACE MOUNT TVS
Features
Mechanical Data
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350 Watts Peak Pulse Power (tp = 8x20 μ s)
IEC 61000-4-2 (ESD): Air – 15kV, Contact – 8kV
IEC 61000-4-4 (EFT): 40A – 5/50ns
IEC 61000-4-5 (Surge): 24A, 8/20 μ s – Level 2(Line-Gnd) & Level
3(Line-Line)
Low Capacitance, typ. = 3 pF
Unidirectional Configuration
Lead Free/RoHS Compliant (Note 4)
“Green” Device (Note 5)
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1
Case: SOD-323
Case Material: Molded Plastic, “Green” Molding Compound,
Note 5. UL Flammability Classification Rating 94V-0
Moisture Sensitivity: Level 1 per J-STD-020
Terminals: Matte Tin Finish annealed over Alloy 42 leadframe
(Lead Free Plating). Solderable per MIL-STD-202, Method 208
Polarity: Cathode Band, See Page 2
Marking Information: See Page 2
Ordering Information: See Page 2
Weight: 0.004 grams (approximate)
2
TOP VIEW
Top View
Device Schematic
Maximum Ratings
@T A = 25°C unless otherwise specified
Characteristic
Peak Pulse Power (tp = 8x20 μ s) (Note 7) T A = 25°C
Symbol
P pk
Value
350
Unit
W
Thermal Characteristics
Characteristic
Thermal Resistance, Junction to Ambient (Note 7) T A = 25°C
Operating and Storage Temperature Range
Symbol
R θ JA
T J , T STG
Value
425
-55 to +150
Unit
° C/W
° C
Electrical Characteristics
@T A = 25°C unless otherwise specified (Note 8)
Reverse
Standoff
Voltage
Breakdown Voltage
V BR @ I T
Test
Current
Max. Reverse Max. Clamping
Leakage @ V RWM Voltage @ I pp = 1A
(Note 6) (Note 3)
Max. Clamping
Voltage V C @ I PP
(Note 3)
Typical Total
Capacitance C T
(Note 1)
V RWM (V)
3.3
Min (V)
4.0
Max (V)
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I T (mA)
1.0
I R ( μ A) V C (V)
5 7
V C (V) I PP (A)
19 20
(pF)
3
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
V R = 0V, f = 1MHz.
tp = 8x20 μ s.
Clamping voltage value is based on an 8x20 μ s peak pulse current (I pp ) waveform (see figure 1).
No purposefully added lead.
Diodes Inc.’s “Green” policy can be found on our website at http://www.diodes.com/products/lead_free/index.php.
Short duration pulse test used to minimize self-heating effect.
Device mounted on FR-4 PC board with suggested pad layout, which can be found on page 3 or on our website at
Positive potential is applied from pin 1 to pin 2.
T3V3LCS3
Document number: DS31104 Rev. 7 - 3
1 of 4
November 2009
? Diodes Incorporated
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